Products   

Commercial Products  
This page lists some of our Commercially available IP cores. Most of our IP cores have been written in a way where they can be easily customized to meet every customer's needs. All cores come with a comprehensive test bench, documentation and sample synthesis scripts.

Our tech support will assist you throughout the entire integration process of our IP in your target device. We will not be satisfied until our IP Core is fully operational in your application.

If you don't see something that will meet your need, please drop us a line to check if we might be working on it already !

Did you know ?

In many cases it is cheaper to have a custom IP core designed specifically for your application, than to buy an of-the-shelf IP Solution ?

Flexible licensing, tailored to your needs is also available !


IpCore & Info 
  • SAS Recorder IP Core
    SAS Recorder IP Core

    The SAS Recorder IP Core provides an ready to use solution for high speed data recording applications. Simple interface guarantees fast time to market solutions.

    Features:
    • High Speed Data Recording
    • Up to 4 Ports
    • SAS 1.5, 3.0, 6.0 and 12.0 Gbps support
    • High Data Bandwidth
    • Hardware managed command sequencing
    • Full SAS interface
    • AXI style streaming data interface
    • Xilinx Transceiver based PHY

    PDF Download Product Brief

  • SAS Initiator IP Core
    SAS Initiator IP Core

    The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacements for the parallel SCSI attachment of mass storage devices. Maximum supported bandwidth is 48 Gbps. The serial link employs multiple high-speed gigabit transceivers.

    Features:
    • SAS & SATA Speed Negotiation and OOB
    • SAS 1.5, 3.0, 6.0 and 12.0 Gbps support
    • SATA 1.5, 3.0 abd 6.0 Gbps support
    • Up to 48 GBps bandwidth
    • Native 32 bit PHY interface
    • Rate Tolerance Management
    • Data and Idle scrambling
    • Frame assembly and decoding
    • Power Management
    • Automatic Identify and Reset Management
    • Automatic Connection Control
    • Support of SMP, SSP and SATA protocols
    • Multi-channel S/G DMA support with on-demand processing
    • 256 bit DATA streaming interface
    • Up to 32 internal transmit buffers
    • Up to 32 internal receive buffers

    PDF Download Product Brief

  • SATA I/II/III Host Controller IP Core
    SATA I/II/III Host Controller IP Core

    The Serial ATA Host Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.

    Features:
    • High Throughput: 531 MBytes/sec Read, 505 MBytes/sec Write
    • Low Latency: 66K IOPS Read, 67K IOPS Write (4k blocks)
    • Connects to SAPIS compliant serial ATA Phy
    • Asynchronous, unrestricted SoC clock, independent of PHY clock
    • Includes Xilinx Transciver based PHY
    • Fully compliant to SATA V3.0 COMPLIANCE CERTIFIED
    • - NCQ
    • - Port Multipliers
    • - Port Selector
    • - FIS based switching
    • Supports Gen 1 (1.5 Gbps), Gen 2 (3,0 Gbps) and Gen 3 (6.0 Gbps)
    • AXI Light interface for register access
    • AXI Stream Interface and for data transfers
    • Full support for PIO, DMA and FPDMA transfers
    • 128 byte (32 double word) data FIFO (optional 256 byte)
    • Implements the shadow register block and the serial ATA status and control registers
    • Parallel ATA legacy software compatibility
    • 48-bit address feature set supported
    • 8b/10b coding and decoding
    • CONT and data scramblers to reduce EMI
    • CRC generation and checking
    • Auto inserted HOLD primitives
    • Power management support (partial and slumber)
    • DMA Support
    • - Descriptor Based Command Processing
    • - Unlimited command list size
    • Many configuration options
    • ucLinux Drivers

    PDF Download Product Brief

  • SATA I/II/III Device Controller IP Core
    SATA I/II/III Device Controller IP Core

    The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.

    Features:
    • 10/20/40 bit Phy interface
    • Connects to SAPIS compliant serial ATA Phy
    • Fully compliant to SATA Gen 1, Gen 2 and Gen 3
    • Wishbone slave interface for register access and FIFO/DMA data transfers
    • Only very few FF's in the Phy clock domain, main part on the Wishbone clock
    • 128 byte (32 double word) data FIFO (optional 256 byte)
    • Parallel ATA legacy software compatibility
    • Implements the Task File, the non-standard serial ATA status and control registers, specific device registers and native mode registers
    • interrupt and DMA handshake (external DMA)
    • 48-bit address feature set supported
    • 8b/10b coding and decoding
    • CONT and data scramblers to reduce EMI
    • CRC generation and checking
    • Auto inserted HOLD primitives
    • Power management support (partial and slumber)
    • Optional native mode programming model
    • Many configuration options

    PDF Download Product Brief

  • USB 3.0 Device IP Core
    USB 3.0 Device IP Core

    A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of a USB Device interface.

    Features:
    • USB 3.0 SuperSpeed support, 5Gbit/s
    • USB 3.0 PIPE interface
    • Integrated DMA engine
    • Up to 16 fully configurable endpoints
    • Bulk, control, interrupt and isochronous endpoints and transfers
    • Full duplex operation support
    • Compact and cost-effective solution

    PDF Download Product Brief

  • USB 2.0 On-The-Go IP Core, Compliance Certified
    USB 2.0 On-The-Go IP Core, Compliance Certified

    A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB device. This USB IP Core supports both Low Speed, Full Speed and High Speed transfers and automatic line speed negotiation.

    Features Include:
    • True Dual-Role capability
    • UTMI+ L2 Interface and ULPI 1.1 wrapper available
    • OTG high performance host mode
    • Full USB peripheral capability
    • Session request protocol support
    • Host negotiation protocol support
    • Low Speed (LS), Full Speed (FS) and High Speed (HS) modes supported
    • Up to 16 endpoints
    • Bulk, interrupt and isochronous transfers
    • Slave and Master WISHBONE i/f (AMBA wrappers available)
    • No dedicated local memory required
    • Compact and cost-effective solution for SoC

    PDF Download Product Brief

  • USB 2.0 Device IP Core HS-Device, Compliance Certified
    USB 2.0 Device IP Core HS-Device, Compliance Certified

    A USB 2.0 Device IP Core that provides high performance small footprint solution for quick and easy implementation of a USB Device interface.

    Features:
    • USB 2.0 high performance operation
    • UTMI+ L2 Interface, ULPI 1.1 wrapper and FS only transceiver interface available
    • Full USB peripheral support
    • High Speed and Full Speed mode support
    • Up to 16 endpoints
    • Bulk, interrupt and isochronous transfers
    • Slave and Master System Interface
    • No dedicated local memory required
    • Compact and cost-effective solution for SoC

    PDF Download Product Brief

  • SD/SDIO/MMC Host IP
    SD/SDIO/MMC Host IP

    A complete, easy to integrate and cost-effective IP core featuring SD/SDIO/MMC Host Controller Interface, for SoC/PDA applications that connect to SD/MMC memory cards and SDIO/combo devices such as Bluetooth device.

    Features:
    • Compliant with SD Host Controller Spec V1.01/1.10
    • Supports SD 1bit and 4bit modes, as well as SPI mode
    • Compatible to MultiMediaCard spec V4.0 and older
    • Provides memory-mapped and i/o access to SD/MMC cards through a Wishbone slave adapter
    • Read cache with variable physical size and configurable page size to boost-up card read access performance.
    • Interrupt-on-completion handshake eliminates host resources utilization during read operations
    • Write FIFO with variable size and configurable thresholds to enable non-blocking operations and prevent back-pressure propagation from card to host
    • Supports posted write operations
    • Supports SDIO IRQ signaling
    • Implements multi-block read and write commands with internal STOP command generation (CMD12) for enhanced throughput
    • Supports any data block length
    • Supports fast and slow SD cards. SD clock frequency: 0-50+MHz
    • Supports hot card insertion and removal
    • SD/SDIO/MMC/SPI identification flow implemented by hardware
    • Provides command port interface for direct access to the SD/MMC devices and for I/O access to SDIO devices
    • Features zero-wait-states on SD bus
    • Wide range of configuration options to fine-tune the core according to the system specifications and demands
    • Wide range of mask able interrupt events, such as card detection, block transfer termination, command completion, error detection end many more
    • No dedicated local memory required

    PDF Download Product Brief

  • SD/SDIO/MMC Target IP
    SD/SDIO/MMC Target IP

    A compact low power and scalable IP core which provides a simple, firmware-friendly cost-effective Physical Link interface for memory, i/o and combo devices, such as SD-based memory cards, Mini SD, Micro SD, SDIO Bluetooth devices, SDIO GPS, MMC memory cards, MMC-RS, MMC-Mobile, CE-ATA devices etc etc.

    Features:
    • SD/SDIO only: Compliant with SD Spec ver1.10 and SDIO Spec ver1.10
    • SD/SDIO only: Supports SD 1bit and 4bit modes, as well as SPI mode
    • SD/SDIO only: 8bit support for future SD spec enhancements
    • SD/SDIO only: Supports SDIO features: Suspend/Resume, Interrupt, Read Wait
    • MMC only: Compliant with MultiMediaCard Spec ver4.X/3.X
    • MMC only: Supports MMC 1bit, 4bit, 8bit modes, as well as SPI mode
    • MMC only: Maximum data rate up to 416Mbits/sec
    • MMC only: Supports Interrupt-mode (Wait-IRQ)
    • MMC only: Supports CEATA specifications (ver1.0), including Completion Signal
    • All command and response types are supported
    • Generic 8/16/32 bit system bus interface
    • Optional extended data buffering 0-4K bytes.
    • Optional read/write data DMA
    • Card-Busy signal asserted by hardware, negated by firmware
    • CRC7 and CRC16 checksum logic
    • Supports data block size of 1 byte to 4K bytes
    • Set of Read-Clear status bits with software interrupt mask
    • Multi-block read and write
    • Stream read and write
    • Built-in Bus Test Procedure
    • Supports fast and slow cards. clock frequency: 0-52+MHz
    • Supports clock suspension
    • Supports hot card insertion and removal
    • Compact and trivial firmware interface

    PDF Download SDIO Product Brief


    PDF Download MMC Product Brief

  • GPON FEC 2.5 Gbps
    GPON FEC 2.5 Gbps

    This high performance core is a full featured Forward Error Correction encoder and decoder, specially designed for high speed optical networks or any other broadband applications. It is fully compliant with the 2.5 Gbps GPON standard (G.984.3) and is available for FPGA or ASIC implementation. The FEC algorithm is based on Reed-Solomon (255,239) code and consists of an encoder and decoder module. The encoder module computes 16 parity bytes and appends them on the 239 byte information block. The decoder receives the 255 bytes codeword, locates and corrects up to 8 byte errors being introduced in the transmission channel.

    Features:
    • Fully compliant with the ITU-T G.984 (GPON), ITU-T G.983 (BPON) and ITU-T G.709 recommendations
    • Supports ASIC and FPGA implementation technologies
    • Single edge, fully synchronous design
    • Area efficient design
    • Symbol rate clock
    • Supports both streaming of data and gaps between codeword bytes
    • Calculates the number of erroneous bytes
    • Generates a status signal indicating error locations
    • Determines the location and magnitude of the erroneous bytes
    • Corrects up to 8 erroneous bytes
    • Detects uncorrectable codewords
    • Predictable low decoder latency

    PDF Download Product Brief

  • Reed Solomon Decoder IP Core
    Reed Solomon Decoder IP Core

    A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error correction. It can be targeted for both ASIC and FPGA technologies.

    Features:
    • Continuous, very high-speed, time-domain Reed-Solomon decoding algorithm.
    • Supports different Reed-Solomon coding standards.
    • Code rate can be dynamically varied
    • Parameterizable bits per symbol (M).
    • Programmable codeword length (NVAL) with parameterizable maximum value (N).
    • Programmable number of errors (TVAL) with parameterizable maximum value (T).
    • Shortened codes supported (NVAL,TVAL).
    • User configured primitive field polynomial.
    • User configured generator polynomial.
    • Synchronous design.
    • Predictable decoder latency.
    • Single or Multiple symbol rate clock (CR).
    • Status and performance monitoring signals

    PDF Download Product Brief

  • Reed Solomon Encoder IP Core
    Reed Solomon Encoder IP Core

    A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error correction. It can be targeted for both ASIC and FPGA technologies.

    Features:
    • Supports different Reed-Solomon coding standards
    • Code rate can be dynamically varied
    • Parameterizable bits per symbol (M)
    • Programmable codeword length (NVAL) with parameterizable maximum value (N)
    • Programmable number of errors (TVAL) with parameterizable maximum value (T)
    • Shortened codes supported (NVAL,TVAL)
    • User configured primitive field polynomial
    • User configured generator polynomial
    • Synchronous design
    • Low latency - 2 cycles
    • Single symbol rate clock

    PDF Download Product Brief

  • Enhanced AES (Rijndael) IP Core
    Enhanced AES (Rijndael) IP Core

    FIPS-197 Compliant. Encrypt and decrypt modules with 128, 192 and 256 bit keys. Various versions are available, from small area to high performance, up to 34Gbit/sec in 0.18u.

    The following building blocks are available for Enhanced AES IP Core:
    • Data Path Module, fully pipelined (single stage)
    • Data Path Module, fully pipelined (dual stage)
    • Static key module (128, 192, 256 bit)
    • Dynamic key module (128, 192, 256 bit)
    Notes: - Data path modules can perform a full cypher/inverse cypher operation every clock cycle. The single stage pipeline version has a latency of 14 cycles, the dual stage pipeline of 24 cycles. - Static key modules need 12 cycles to expand a key, dynamic key modules can generate a new key every clock cycle.

  • I2C Master and Slave
    I2C Master and Slave

    I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.

    The interface defines 3 transmission speeds:
    • Normal: 100Kbps
    • Fast: 400Kbps
    • High speed: 3.5Mbps

    Features:
    • Compatible with Philips I2C standard
    • Multimaster Operation
    • Software programmable clock frequency
    • Clock Stretching and Wait state generation
    • Software programmable acknowledge bit
    • Interrupt or bit-polling driven byte-by-byte data-transfers
    • Arbitration lost interrupt, with automatic switching from master to slave
    • Called as Slave interrupt
    • Start/Stop/Repeated Start generation
    • Acknowledge bit generation/detection
    • Start/Stop detection
    • Bus busy detection
    • Supports 7 and 10bit addressing mode in both master and slave modes
    • Operates from a wide range of input clock frequencies
    • Static synchronous design
    • Fully synthesizable

  • ATA7 (UDMA 133) Host IP
    ATA7 (UDMA 133) Host IP

    A ATA-7 compliant host controller core to interface to ATA devices like hard-disks, CD and DVD drives. This core is targeted for SOC implementations in ASIC and FPGA.

    Features:
    • PIO modes 0-4
    • Multi-word DMA modes 0-2
    • Ultra DMA modes 0-6
    • Programmable timings for PIO and DMA modes
    • Support for Ultra DMA pause and termination
    • Standard slave Wishbone interface to microprocessor/microcontroller
    • Interrupt generator for IRQ driven software driver implementation
    • Transparent (pass through) access from processor interface to device task registers
    • DMA engine and master Wishbone interface for data transfer
    • Small register FIFOs for transmit and receive data
    • 66MHz clock for UDMA133 (mode 6) operation

    PDF Download Product Brief

  • ATA7 (UDMA 133) Target IP
    ATA7 (UDMA 133) Target IP

    This is a ATA-7 compliant device interface core used for interfacing custom devices to IDE controller. Core is targeted for SOC implementations in ASIC and FPGA.

    Features:
    • PIO modes 0-4
    • IORDY signaling for PIO cycle extension
    • Multi-word DMA modes 0-2
    • Ultra DMA modes 0-6
    • Programmable timings for PIO and DMA modes
    • Support for Ultra DMA pause and termination
    • Standard slave Wishbone interface to microprocessor/microcontroller
    • Interrupt generator for IRQ driven software driver implementation
    • Automatic handling of BSY and DRQ bits
    • DMA engine and master Wishbone interface for data transfer
    • Small register FIFOs for transmit and receive data
    • Acts as a single, master ATA/ATAPI device on ATA cable
    • 66MHz clock for UDMA133 (mode 6) operation

    PDF Download Product Brief

All ASICS World Services,LTD. IP Cores Support The Following Busses :
AXI | AHB | AVALON | WISHBONE | CUSTOM