SATA I/II/III Device Controller IP Core

The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.


  • 10/20/40 bit Phy interface
  • Connects to SAPIS compliant serial ATA Phy
  • Fully compliant to SATA Gen 1, Gen 2 and Gen 3
  • Wishbone slave interface for register access and FIFO/DMA data transfers
  • Only very few FF’s in the Phy clock domain, main part on the Wishbone clock
  • 128 byte (32 double word) data FIFO (optional 256 byte)
  • Parallel ATA legacy software compatibility
  • Implements the Task File, the non-standard serial ATA status and control registers, specific device registers and native mode registers
  • interrupt and DMA handshake (external DMA)
  • 48-bit address feature set supported
  • 8b/10b coding and decoding
  • CONT and data scramblers to reduce EMI
  • CRC generation and checking
  • Auto inserted HOLD primitives
  • Power management support (partial and slumber)
  • Optional native mode programming model
  • Many configuration options

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