Free ip cores
The following is a list of free IP Cores developed by ASICS.ws. These IP cores have been deposited at OpenCores for free download. Please email us if you need to have an IP core modified or adjusted to meet your needs.
Most of our IP Cores feature the WISHBONE SoC bus. This is an Open and Free SoC bus. To find out more about the WISHBONE SoC bus please visits it's home page. All Free IP Cores are distributed under a modified BSD
for Resume style license.
Please Note: We provide full technical support for most IP Cores featured on the OpenCores web site. Please email us with specific inquiries.
Most of our IP Cores feature the WISHBONE SoC bus. This is an Open and Free SoC bus. To find out more about the WISHBONE SoC bus please visits it's home page. All Free IP Cores are distributed under a modified BSD

This is the Entire License for all of our Free IP Cores.
Copyright (C) 2000-2009, ASICs World Services, LTD. , AUTHORS
All rights reserved.
Redistribution and use in source, netlist, binary and silicon forms, with or without modification, are permitted provided that the following conditions are met:
X
- Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
- Neither the name of ASICS World Services, the Authors and/or the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
S.No | IP Core | FPGA | ASIC | WISH BONE | OTHER I/F | ![]() |
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Networking, Communications, Connectivity | 1 | USB 1.1 Phy | ![]() |
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USB, UTMI | ![]() |
![]() USB 1.1 Phy
USB 1.1 Physical Interface core. This core provides all functions essential to interface to the USB 1.1 bus. This includes serial/parallel conversion, bit stuffing and unstuffing, NRZI encoding and decoding and a DPLL. It comes with a industry standard UTMI interface for easy portability
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2 | USB 1.1 Device IP Core | ![]() |
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UTMI | ![]() |
![]() USB 1.1 Device IP Core
USB 1.1 compliant device core. Internally it provides a very easy to use FIFO interface, externally it features a UTMI interface to hock up a USB 1.1 compatible PHY. This core performs all USB required enumeration in hardware. There is no need for an additional microcontroler. It stores device and configuration descriptors in a ROM.
Sample Implementation Results
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
3 | USB 2.0 Device IP Core | ![]() |
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UTMI | ![]() USB 2.0 Device IP Core
A USB 2.0 compliant device controller. Provides transfer speeds of over 480Mbps. Easy integration in to an existing system utilizing WISHBONE bus interface. Provides UTMI interface for easy PHY integration (internally or externally).
Sample Implementation Results
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4 | Asynchronous Serial IO Controller | ![]() |
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RS232 | ![]() |
![]() Asynchronous Serial IO Controller
Very simple serial interface core. Provides hardware handshake (RTS & CTS), and a fixed 1 start, 1 stop bit data format. Internal interface is through 4 byte deep FIFOs.
Sample Implementation Results
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5 | Single Slot PCM Controller | ![]() |
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TDMI | ![]() |
![]() Single Slot PCM Controller
This core provides a slave interface to a single slot PCM stream. It captures and transmits 16 bit samples a the SYNC interval. Allows to interface to such popular devices like TI DSPs (via McBSP bus) in PCM mode
Sample Implementation Results
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6 | AC97 Controller IP Core | ![]() |
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AC97 | ![]() |
![]() AC97 Controller IP Core
This core provides an easy interface to AC97 Audio Codecs. It supports variable and fixed sample rates, 16-20 bits sample sizes, and full 6 channel audio. It is WISHBONE compliant and can directly interface to an external DMA engine.
Sample Implementation Results
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7 | I2C Master Controller | ![]() |
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I2C | ![]() |
![]() I2C Master Controller
Implements a master interface to the famous I2C bus from Philips (compatible with SMBus). Supports single and multi master operations, clock stretching, polled and interrupt driven operations. Can perform 7 or 10 bit addressing. Timing is user programmable.
Sample Implementation Results
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8 | ATA/ATAPI Host Controller | ![]() |
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ATA, ATAPI | ![]() |
![]() ATA/ATAPI Host Controller
This Core provides direct interface to ATA compliant devices, such as Hard Drives, CDROMs, PC-Cards, Compact Flash, etc. Three versions of this core are available depending on your needs. Choose from a very simple and small single device version to a full featured version with DMA support.
Sample Implementation Results for OCIDEC-1 This version supports PIO transfer only. It provides a single timing register for all accesses to the connected devices.
Sample Implementation Results for OCIDEC-2 This version supports PIO transfer only. It provides common timing register for all compatible accesses to the connected devices. And separate timing register per device for fast DataPort accesses.
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9 | Motorola DragonBall/68K to Wishbone Bridge | ![]() |
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Mot. 68K/ DragonBall | ![]() |
![]() Motorola DragonBall/68K to Wishbone Bridge
This is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full featured 16bit Wishbone master bus.
Features
16bit Motorola DragonBall/68K Interface
16bit full featured RevB.3 Wishbone Classic Master interface
Programmable address-bus size
Static synchronous design
Fully synthesisable
Sample Implementation Results
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10 | Enhanced Motorola MC68HC11 SPI IP Core | ![]() |
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Mot. MC68HC11 SPI Po | ![]() Enhanced Motorola MC68HC11 SPI IP Core
Enhanced version of the Serial Peripheral Interface available on Motorola's MC68HC11 family of CPUs. Enhancements include a wider supported operating frequency range, 4 deep read and write FIFOs, and programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase (CPHA) and clock polarity (CPOL). The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances. Very simple, very small.
Features 4 entries deep read FIFO 4 entries deep write FIFO Interrupt generation after 1, 2, 3, or 4 transfered bytes Static synchronous design Fully synthesizable Sample Implementation Results
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
CPU, DSP, uControllers, etc. | 1 | Mini-Risc CPU/Microcontroller (PIC Clone) IP Core | ![]() |
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3 x 8bit I/O Ports | ![]() |
![]() Mini-Risc CPU/Microcontroller (PIC Clone) IP Core
A small micro controller IP core compatible with the popular Microchip PIC16C57. This implementation executes one instruction per cycle. This version has 3x 8 bit I/O ports and up to 2K instruction memory.
Sample Implementation Results
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2 | Open 54x DSP clone | ![]() |
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![]() Open 54x DSP clone
The goal of this project is to build a TI 54x DSP compatible IP core. It will utilize a 5 stage pipeline and have 4 external WISHBONE interfaces for maximum performance.
Sample Implementation Results
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Encryption / Decryption | 1 | DES IP Core | ![]() |
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![]() DES IP Core
Traditional DES engine. Two versions are provided, an area optimized and a performance optimized.
The Area Optimized (CBC Mode) version needs 16 cycles to complete a full encryption/decryption cycle.
The Performance Optimized (EBC Mode) version is a pipelined implementation that has a 16 cycle pipeline (plus 1 input and 1 output register). It can perform a complete encryption/decryption every cycle.
Sample Implementation Results Area Optimized Version
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2 | Triple DES | ![]() |
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![]() Triple DES
Triple DES engine. Two versions are provided, an area optimized and a performance optimized.
The Area Optimized (CBC Mode) version needs 48 cycles to complete a full encryption/decryption cycle.
The Performance Optimized (EBC Mode) version is a pipelined implementation that has a 48 cycle pipeline (plus 1 input and 1 output register). It can perform a complete encryption/decryption every cycle.
Sample Implementation Results Area Optimized Version
Sample Implementation Results Performance Optimized Version
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
3 | AES (Rijndael) IP Core | ![]() |
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![]() AES (Rijndael) IP Core
Simple AES Rijndael Crypto IP Core. This implementation was designed with the goal in mind that it should fit in to a low cost FPGA (such as a Spartan IIe from Xilinx) and provide reasonable performance.
The Free version comes with a 128 key expansion module only. Other Implementations of the AES Rijndael IP core with different key sizes (192 & 256 bit) and performance attributes (like a fully pipelined ultra-high-speed version) are commercially available from ASICS.ws. Pleaseemail us for more information.
Sample Implementation Results for Cipher Block
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Math / Arithmetic Cores | 1 | Single Precision FPU (IEEE-754 compliant) IP Core | ![]() |
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![]() Single Precision FPU (IEEE-754 compliant) IP Core
This is a IEEE754 compliant single precision floating point unit. It has a 4 stage pipeline and can execute an operation every clock cycle. It includes Add, Subtract, Multiply and Divide operations, supports rounding to Nearest Even, Round to Zero, Round to +INF and Round to -INF.
Sample Implementation Results
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2 | CORDIC Core | ![]() |
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![]() CORDIC Core
The CORDIC algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.
Sample Implementation Results
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3 | Hardware Dividers | ![]() |
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![]() Hardware Dividers
This is a collection of several dividers. All dividers are fully synthesizabel and parameterized. All dividers are pipelined and can perform an operation every clock cycle.
Sample Implementation Results
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4 | 8x8 DCT, fully pipelined | ![]() |
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![]() 8x8 DCT, fully pipelined
This is a fully pipelined, parallel implementation of an 8x8 DCT Unit. It can generate a DCT result every clock cycle, or an entire 8x8 DCT transform in 64 clock cycles. This is an equivalent of 4096 MAC operations per clock cycle. The amount of bits per coefficient is parameterized. The output of the DCT unit is already in the zig-zag format described in the JPEG, MPEG, and other standards.
Sample Implementation Results
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
5 | QNR, Quantization | ![]() |
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![]() QNR, Quantization
This is a Quantization & Rounding Unit as described in the JPEG, MPEG, and other specs. It is fully pipelined and can generate a result every clock cycle.
Sample Implementation Results
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
6 | Huffman Encoder | ![]() |
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![]() Huffman Encoder
This is an Huffman based entropy encoder as described in the JPEG, MPEG and other specs. It transforms an input stream into a Huffman encoded output stream. Included in the design are JPEG's default Huffman tables for DC-luminance, DC-chrominance, AC-luminance, and AC-chrominance.
Sample Implementation Results
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
7 | Huffman Decoder | ![]() |
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![]() Huffman Decoder
This is an Huffman based entropy decoder as described in the JPEG, MPEG and other specs. It transforms a Huffman encoded input stream into a decoded output stream. Included in the design are JPEG's default Huffman tables for DC-luminance, DC-chrominance, AC-luminance, and AC-chrominance.
Sample Implementation Results
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
Misc. Building Blocks | 1 | Generic FIFOs | ![]() |
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![]() Generic FIFOs
Generic FIFOs that are shared between various projects. Fully parametarized, multi purpose implementations.
Sample Implementation Results
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2 | DMA/Bridge IP Core | ![]() |
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![]() DMA/Bridge IP Core
This DMA engine has two WISHBONE interfaces and can perform DMA transfers on either one of the two interfaces or act as a passive bridge. It features up to 31 channels, and up to 8 priority levels. Different buffer molds may be selected: Linear Access, Circular Buffers, and FIFO Buffers. It also provides Linked List Descriptors support in hardware. Further it supports hardware handshake and interrupts.
Sample Implementation Results
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
3 | WISHBONE Interconnect Matrix | ![]() |
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![]() WISHBONE Interconnect Matrix
This core provides an easy way to integrate numerous cores to create a SoC. It acts as a interconnect matrix and arbiter between up to 8 masters and 16 slaves. It provides up to 4 priority levels in it's arbiters and is fully configurable.
Sample Implementation Results
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
4 | Simple General Purpose IO | ![]() |
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8 bit GPIO | ![]() |
![]() Simple General Purpose IO
Simple General Purpose IO port. It supports up to 8 GPIO pins. Each pin is individually programmable as either input or output. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances (e.g. 4 simple GPIO cores provide a 32bit wishbone interface). Very simple, very small.
Features
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
5 | Simple Programmable Interrupt Controller | ![]() |
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8 interrupt sources | ![]() |
![]() Simple Programmable Interrupt Controller
Simple programmable interrupt controller. It supports up to 8 interrupt sources. Polarity and sensitivity (either edge or level) is programmable per interrupt source. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances. Very simple, very small.
Features Sample Implementation Results
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6 | WISHBONE to OPB and OPB to WISHBONE wrappers (for Xilinx EDK only) | ![]() |
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OPB | ![]() |
![]() WISHBONE to OPB and OPB to WISHBONE wrappers (for Xilinx EDK only)
WISHBONE to OPB Bus Interface wrapper and OPB to WISHBONE Bus Interface wrapper provide an straight forward way to access peripherals that where written for WISHBONE on OPB bus and peripherals that have been written for OPB on a WISHBONE bus. Very simple, very small.
Address space is direct mapped, allowing transparent access.
Sample Implementation Results
Currently this IP Core is available as a pluggin for Xilinx EDK (netlist) only. Please email us if you need to have an IP Core translated to a different language. You can download this IP Core X |
Memory Controllers, Interfaces | 1 | Advanced Memory Controller IP Core | ![]() |
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SDRAM, SSRAM, FLASH | ![]() |
![]() Advanced Memory Controller IP Core
The memory Controller supports SDRAM, SSRAM, FLASH, ROM and other asynchronous and synchronous devices. It comes with 8 chip selects, and is fully programmable. Full support of burst operations as well as other special features such as leaving banks and rows open for increased performance. Dynamic bus sizing allows booting from 8 or 16 bit devices (such as flash).
Sample Implementation Results
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2 | SSRAM Interface | ![]() |
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SSRAM | ![]() |
![]() SSRAM Interface
This core provides an advanced interface to ZBT SSRAMs.
Sample Implementation Results
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |
Video (CRT, LCD) Controllers, Interfaces, etc. | 1 | VGA/LCD Controller | ![]() |
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RGB | ![]() |
![]() VGA/LCD Controller
Advanced interface for CRT and LCD monitors. Video timing is fully user programmable. Hardware support for 32, 24, and 16 bit color modes, as well as 8 bit gray scale and 8 bit pseudo color modes. Bank switching, triple display and two hardware cursor support also included.
Sample Implementation Results
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2 | Video Compression System | ![]() |
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![]() Video Compression System
The Video Compression System project will include a variety of IP Cores to enable the end user to build various compression systems, such as MPEG-1, MPEG-2 and MPEG-4. As well as to provide support for H.310, H.320 etc. It will also include JPEG and Motion JPEG codecs.
Sample Implementation Results
Currently this IP Core is available in Verilog only. Please email us if you need to have an IP Core translated to a different language. To find out more about this IP Core and/or to download the full sources and documentation please visit the Project Page X |