This is a high performance, small footprint ZLIB compatible IP Core. It features 3 DMA engines, AXI interconnect and separate clocks for AXI interfaces and compression/decompression engines.
Features:
- 100% ZLIB compatible
- Fixed Huffman encoding
- Subset of LZ77
- Scatter/Gather DMA engine
- Utilizes linked list of transfer descriptors
- Compression and Decompression in one IP Core
- Configurable Data Path to 32, 64 or 128 bit
- Fully AXI-4 compatible
- AXI-Light for register Interface
- Separate clocks for engines and AXI interface
