ATA7 (UDMA 133) Target IP

This is a ATA-7 compliant device interface core used for interfacing custom devices to IDE controller. Core is targeted for SOC implementations in ASIC and FPGA.


  • PIO modes 0-4
  • IORDY signaling for PIO cycle extension
  • Multi-word DMA modes 0-2
  • Ultra DMA modes 0-6
  • Programmable timings for PIO and DMA modes
  • Support for Ultra DMA pause and termination
  • Standard slave Wishbone interface to microprocessor/microcontroller
  • Interrupt generator for IRQ driven software driver implementation
  • Automatic handling of BSY and DRQ bits
  • DMA engine and master Wishbone interface for data transfer
  • Small register FIFOs for transmit and receive data
  • Acts as a single, master ATA/ATAPI device on ATA cable
  • 66MHz clock for UDMA133 (mode 6) operation

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