A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error correction. It can be targeted for both ASIC and FPGA technologies.
Features:
- Continuous, very high-speed, time-domain Reed-Solomon decoding algorithm.
- Supports different Reed-Solomon coding standards.
- Code rate can be dynamically varied
- Parameterizable bits per symbol (M).
- Programmable codeword length (NVAL) with parameterizable maximum value (N).
- Programmable number of errors (TVAL) with parameterizable maximum value (T).
- Shortened codes supported (NVAL,TVAL).
- User configured primitive field polynomial.
- User configured generator polynomial.
- Synchronous design.
- Predictable decoder latency.
- Single or Multiple symbol rate clock (CR).
- Status and performance monitoring signals
