{"id":15,"date":"2014-09-29T10:41:51","date_gmt":"2014-09-29T10:41:51","guid":{"rendered":"http:\/\/asics.ws\/v6\/?page_id=15"},"modified":"2016-02-06T12:10:40","modified_gmt":"2016-02-06T12:10:40","slug":"about-us","status":"publish","type":"page","link":"https:\/\/asics.ws\/v6\/about-us\/","title":{"rendered":"About us"},"content":{"rendered":"

ASICS World Services provides a broad line of general-purpose IP cores, including a variety of USB related products such as USB 2.0 OTG IP Cores as well as various others such as SATA I\/II\/III IP Core, encryption (AES), error correction (Reed Solomon), and many other functions.<\/p>\n

ASICS World Services was conceived and founded in 1999, immediately starting to offer various products and services. Since then ASICS World Services has established a world wide reputation for professional highest-quality IP Cores with flexible licensing at a low cost.<\/p>\n

The engineering team is made up of highly experienced senior engineers who have been in the digital design environment for 12-25 years prior to joining ASICS World Services. Rapidly expanding customer base is quickly promoting ASICS World services to one of the leading IP providers in the world.
\n <\/p>\n

Business Model<\/div>\n

ASICS.ws has changed it’s original plan from being just an IP core provider, to also provide OPEN and FREE IP cores.<\/p>\n

What does OPEN and FREE mean in this context ?<\/div>\n

It means that some IP cores are provided at no charge. All source code and documentation can be freely downloaded. You don’t even have to register with ASICS.ws, just download the sources from OpenCores.org.<\/p>\n

How do we stay in business ?<\/div>\n

ASICS.ws is trying to incorporate the model of the software industry to IP cores. Get the IP core for free, but if you need help, pay for support. In addition, some of our IP cores will not be publicly available for free download, but only to registered customers. That will aid us to keep a leading edge on our innovative solutions.<\/p>\n

Most IP cores sell today well above the $100,000 mark. Each time a company purchases one of those high priced IP cores, they take a large risk. Sure, the financial side might be protected through contracts, but how about the lost time-to-market ? Who will put a value on that ? With our cores, customers see from the beginning what we have to offer and can experience the superior quality of our IP cores without paying a penny.<\/p>\n

 
\n <\/p>\n

ASICS.ws has dedicated Distributors in the following Countries\/States:
\n <\/p>\n

Worldwide<\/div>\n
ASICS World Services, LTD.<\/div>\n

 
\ninfo@asics.ws<\/a>
\n 
\n <\/p>\n

USA<\/div>\n

\"hitech_logo_2\"<\/p>\n

HiTech Global Distribution, LLC
\ninfo@hitechglobal.com<\/a>
\nTel: +1 408 781-8043
\nFax: +1 408 268-4173<\/p>\n

 
\n 
\n <\/p>\n

Distributors Wanted !<\/p>\n","protected":false},"excerpt":{"rendered":"

ASICS World Services provides a broad line of general-purpose IP cores, including a variety of USB related products such as USB 2.0 OTG IP Cores as well as various others such as SATA I\/II\/III IP Core, encryption (AES), error correction (Reed Solomon), and many other functions. ASICS World Services was conceived and founded in 1999, […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"acf":[],"yoast_head":"\nAbout us - ASICS.ws - Your Partner for IP Cores, ASIC\/FPGA Design, Synthesis and Verification-<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/asics.ws\/v6\/about-us\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"About us - ASICS.ws - Your Partner for IP Cores, ASIC\/FPGA Design, Synthesis and Verification-\" \/>\n<meta property=\"og:description\" content=\"ASICS World Services provides a broad line of general-purpose IP cores, including a variety of USB related products such as USB 2.0 OTG IP Cores as well as various others such as SATA I\/II\/III IP Core, encryption (AES), error correction (Reed Solomon), and many other functions. ASICS World Services was conceived and founded in 1999, […]\" \/>\n<meta property=\"og:url\" content=\"https:\/\/asics.ws\/v6\/about-us\/\" \/>\n<meta property=\"og:site_name\" content=\"ASICS.ws - Your Partner for IP Cores, ASIC\/FPGA Design, Synthesis and Verification-\" \/>\n<meta property=\"article:modified_time\" content=\"2016-02-06T12:10:40+00:00\" \/>\n<meta property=\"og:image\" content=\"http:\/\/asics.ws\/v6\/wp-content\/uploads\/2014\/09\/hitech_logo_2.jpg\" \/>\n<meta name=\"twitter:label1\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data1\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebSite\",\"@id\":\"http:\/\/asics.ws\/v6\/#website\",\"url\":\"http:\/\/asics.ws\/v6\/\",\"name\":\"ASICS.ws - Your Partner for IP Cores, ASIC\/FPGA Design, Synthesis and Verification-\",\"description\":\"ASICS and FPGA IP Cores, and Design, Verification and Synthesis services\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"http:\/\/asics.ws\/v6\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"en-US\"},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/asics.ws\/v6\/about-us\/#primaryimage\",\"url\":\"http:\/\/asics.ws\/v6\/wp-content\/uploads\/2014\/09\/hitech_logo_2.jpg\",\"contentUrl\":\"http:\/\/asics.ws\/v6\/wp-content\/uploads\/2014\/09\/hitech_logo_2.jpg\"},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/asics.ws\/v6\/about-us\/\",\"url\":\"https:\/\/asics.ws\/v6\/about-us\/\",\"name\":\"About us - ASICS.ws - Your Partner for IP Cores, ASIC\/FPGA Design, Synthesis and Verification-\",\"isPartOf\":{\"@id\":\"http:\/\/asics.ws\/v6\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\/\/asics.ws\/v6\/about-us\/#primaryimage\"},\"datePublished\":\"2014-09-29T10:41:51+00:00\",\"dateModified\":\"2016-02-06T12:10:40+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/asics.ws\/v6\/about-us\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/asics.ws\/v6\/about-us\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/asics.ws\/v6\/about-us\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"http:\/\/asics.ws\/v6\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"About us\"}]}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"About us - ASICS.ws - Your Partner for IP Cores, ASIC\/FPGA Design, Synthesis and Verification-","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/asics.ws\/v6\/about-us\/","og_locale":"en_US","og_type":"article","og_title":"About us - ASICS.ws - Your Partner for IP Cores, ASIC\/FPGA Design, Synthesis and Verification-","og_description":"ASICS World Services provides a broad line of general-purpose IP cores, including a variety of USB related products such as USB 2.0 OTG IP Cores as well as various others such as SATA I\/II\/III IP Core, encryption (AES), error correction (Reed Solomon), and many other functions. ASICS World Services was conceived and founded in 1999, […]","og_url":"https:\/\/asics.ws\/v6\/about-us\/","og_site_name":"ASICS.ws - Your Partner for IP Cores, ASIC\/FPGA Design, Synthesis and Verification-","article_modified_time":"2016-02-06T12:10:40+00:00","og_image":[{"url":"http:\/\/asics.ws\/v6\/wp-content\/uploads\/2014\/09\/hitech_logo_2.jpg"}],"twitter_misc":{"Est. reading time":"2 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebSite","@id":"http:\/\/asics.ws\/v6\/#website","url":"http:\/\/asics.ws\/v6\/","name":"ASICS.ws - Your Partner for IP Cores, ASIC\/FPGA Design, Synthesis and Verification-","description":"ASICS and FPGA IP Cores, and Design, Verification and Synthesis services","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"http:\/\/asics.ws\/v6\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"en-US"},{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/asics.ws\/v6\/about-us\/#primaryimage","url":"http:\/\/asics.ws\/v6\/wp-content\/uploads\/2014\/09\/hitech_logo_2.jpg","contentUrl":"http:\/\/asics.ws\/v6\/wp-content\/uploads\/2014\/09\/hitech_logo_2.jpg"},{"@type":"WebPage","@id":"https:\/\/asics.ws\/v6\/about-us\/","url":"https:\/\/asics.ws\/v6\/about-us\/","name":"About us - ASICS.ws - Your Partner for IP Cores, ASIC\/FPGA Design, Synthesis and Verification-","isPartOf":{"@id":"http:\/\/asics.ws\/v6\/#website"},"primaryImageOfPage":{"@id":"https:\/\/asics.ws\/v6\/about-us\/#primaryimage"},"datePublished":"2014-09-29T10:41:51+00:00","dateModified":"2016-02-06T12:10:40+00:00","breadcrumb":{"@id":"https:\/\/asics.ws\/v6\/about-us\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/asics.ws\/v6\/about-us\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/asics.ws\/v6\/about-us\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"http:\/\/asics.ws\/v6\/"},{"@type":"ListItem","position":2,"name":"About us"}]}]}},"_links":{"self":[{"href":"https:\/\/asics.ws\/v6\/wp-json\/wp\/v2\/pages\/15"}],"collection":[{"href":"https:\/\/asics.ws\/v6\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/asics.ws\/v6\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/asics.ws\/v6\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/asics.ws\/v6\/wp-json\/wp\/v2\/comments?post=15"}],"version-history":[{"count":38,"href":"https:\/\/asics.ws\/v6\/wp-json\/wp\/v2\/pages\/15\/revisions"}],"predecessor-version":[{"id":302,"href":"https:\/\/asics.ws\/v6\/wp-json\/wp\/v2\/pages\/15\/revisions\/302"}],"wp:attachment":[{"href":"https:\/\/asics.ws\/v6\/wp-json\/wp\/v2\/media?parent=15"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}