Commercial Products

IP Core	Info
USB 3.0 Device IP Core
SATA I/II/III Device Controller IP Core
SATA I/II/III Host Controller IP Core
ATA7 (UDMA 133) Host IP
ATA7 (UDMA 133) Target IP
SPI Flash Controller
SD/SDIO/MMC Target IP
GPON FEC 2.5 Gbps
SD/SDIO/MMC Host IP
I2C Master and Slave
USB 2.0 Device IP Core HS-Device Certified
Reed Solomon Encoder IP Core
Reed Solomon Decoder IP Core
AMBA AHB - WISHBONE Wrapper IP Core
USB 2.0 On-The-Go IP Core (LS, FS & HS) HS-OTG Certified
16 Bit RISC DSP Soft IP Core
16 Bit RISC MCU Soft IP Core
Enhanced AES (Rijndael) IP Core
Enhanced Floating Point Unit

USB 3.0 Device IP Core A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of a USB Device interface. Features: USB 3.0 SuperSpeed support, 5Gbit/s USB 3.0 PIPE interface Integrated DMA engine Up to 16 fully configurable endpoints Bulk, control, interrupt and isochronous endpoints and transfers Full duplex operation support Compact and cost-effective solution Download Product Brief

SATA I/II/III Device IP Core The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding. Features: 10/20/40 bit Phy interface Connects to SAPIS compliant serial ATA Phy Fully compliant to SATA Gen 1, Gen 2 and Gen 3 Wishbone slave interface for register access and FIFO/DMA data transfers Only very few FF's in the Phy clock domain, main part on the Wishbone clock 128 byte (32 double word) data FIFO (optional 256 byte) Parallel ATA legacy software compatibility Implements the Task File, the non-standard serial ATA status and control registers, specific device registers and native mode registers interrupt and DMA handshake (external DMA) 48-bit address feature set supported 8b/10b coding and decoding CONT and data scramblers to reduce EMI CRC generation and checking Auto inserted HOLD primitives Power management support (partial and slumber) Optional native mode programming model Many configuration options Download Product Brief

SATA I/II/III Host IP Core The Serial ATA Host Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding. Features: 10/20/40 bit Phy interface Connects to SAPIS compliant serial ATA Phy Fully compliant to SATA Gen 1, Gen 2 and Gen 3 Wishbone slave interface for register access and FIFO/DMA data transfers Only very few FF's in the Phy clock domain, main part on the Wishbone clock 128 byte (32 double word) data FIFO (optional 256 byte) Parallel ATA legacy software compatibility Implements the Task File, the non-standard serial ATA status and control registers, specific device registers and native mode registers interrupt and DMA handshake (external DMA) 48-bit address feature set supported 8b/10b coding and decoding CONT and data scramblers to reduce EMI CRC generation and checking Auto inserted HOLD primitives Power management support (partial and slumber) Optional native mode programming model Many configuration options Download Product Brief

ATA7 Host IP Core A ATA-7 compliant host controller core to interface to ATA devices like hard-disks, CD and DVD drives. This core is targeted for SOC implementations in ASIC and FPGA. Features: PIO modes 0-4 Multi-word DMA modes 0-2 Ultra DMA modes 0-6 Programmable timings for PIO and DMA modes Support for Ultra DMA pause and termination Standard slave Wishbone interface to microprocessor/microcontroller Interrupt generator for IRQ driven software driver implementation Transparent (pass through) access from processor interface to device task registers DMA engine and master Wishbone interface for data transfer Small register FIFOs for transmit and receive data 66MHz clock for UDMA133 (mode 6) operation Download Product Brief

ATA7 Target IP Core This is a ATA-7 compliant device interface core used for interfacing custom devices to IDE controller. Core is targeted for SOC implementations in ASIC and FPGA. Features: PIO modes 0-4 IORDY signaling for PIO cycle extension Multi-word DMA modes 0-2 Ultra DMA modes 0-6 Programmable timings for PIO and DMA modes Support for Ultra DMA pause and termination Standard slave Wishbone interface to microprocessor/microcontroller Interrupt generator for IRQ driven software driver implementation Automatic handling of BSY and DRQ bits DMA engine and master Wishbone interface for data transfer Small register FIFOs for transmit and receive data Acts as a single, master ATA/ATAPI device on ATA cable 66MHz clock for UDMA133 (mode 6) operation Download Product Brief

SPI Flash Controller The SPI FLASH controller provides an simple interface to serial FLASH devices, which are memory mapped in to the SoC memory space. Features: Supports up to 8 FLASH Devices on a single SPI bus Supports FLASH devices up to 16MBytes each Flash is directly memory mapped in to the SoC memory space Supports high speed FLASH devices, up to 50 Mhz Can directly boot from FLASH after power on Software assistant FLASH programming Download Product Brief

SD/SDIO/MMC Device IP Core A compact low power and scalable IP core which provides a simple, firmware-friendly cost-effective Physical Link interface for memory, i/o and combo devices, such as SD-based memory cards, Mini SD, Micro SD, SDIO Bluetooth devices, SDIO GPS, MMC memory cards, MMC-RS, MMC-Mobile, CE-ATA devices etc etc. Features: SD/SDIO only: Compliant with SD Spec ver1.10 and SDIO Spec ver1.10 SD/SDIO only: Supports SD 1bit and 4bit modes, as well as SPI mode SD/SDIO only: 8bit support for future SD spec enhancements SD/SDIO only: Supports SDIO features: Suspend/Resume, Interrupt, Read Wait MMC only: Compliant with MultiMediaCard Spec ver4.X/3.X MMC only: Supports MMC 1bit, 4bit, 8bit modes, as well as SPI mode MMC only: Maximum data rate up to 416Mbits/sec MMC only: Supports Interrupt-mode (Wait-IRQ) MMC only: Supports CEATA specifications (ver1.0), including Completion Signal All command and response types are supported Generic 8/16/32 bit system bus interface Optional extended data buffering 0-4K bytes. Optional read/write data DMA Card-Busy signal asserted by hardware, negated by firmware CRC7 and CRC16 checksum logic Supports data block size of 1 byte to 4K bytes Set of Read-Clear status bits with software interrupt mask Multi-block read and write Stream read and write Built-in Bus Test Procedure Supports fast and slow cards. clock frequency: 0-52+MHz Supports clock suspension Supports hot card insertion and removal Compact and trivial firmware interface Download MMC Target Product Brief Download SD/SDIO Target Product Brief

GPON FEC 2.5 Gbps This high performance core is a full featured Forward Error Correction encoder and decoder, specially designed for high speed optical networks or any other broadband applications. It is fully compliant with the 2.5 Gbps GPON standard (G.984.3) and is available for FPGA or ASIC implementation. The FEC algorithm is based on Reed-Solomon (255,239) code and consists of an encoder and decoder module. The encoder module computes 16 parity bytes and appends them on the 239 byte information block. The decoder receives the 255 bytes codeword, locates and corrects up to 8 byte errors being introduced in the transmission channel. Features: Fully compliant with the ITU-T G.984 (GPON), ITU-T G.983 (BPON) and ITU-T G.709 recommendations Supports ASIC and FPGA implementation technologies Single edge, fully synchronous design Area efficient design Symbol rate clock Supports both streaming of data and gaps between codeword bytes Calculates the number of erroneous bytes Generates a status signal indicating error locations Determines the location and magnitude of the erroneous bytes Corrects up to 8 erroneous bytes Detects uncorrectable codewords Predictable low decoder latency Download Product Brief

SD/SDIO/MMC Host IP A complete, easy to integrate and cost-effective IP core featuring SD/SDIO/MMC Host Controller Interface, for SoC/PDA applications that connect to SD/MMC memory cards and SDIO/combo devices such as Bluetooth device. Features: Compliant with SD Host Controller Spec V1.01/1.10 Supports SD 1bit and 4bit modes, as well as SPI mode Compatible to MultiMediaCard spec V4.0 and older Provides memory-mapped and i/o access to SD/MMC cards through a Wishbone slave adapter Read cache with variable physical size and configurable page size to boost-up card read access performance. Interrupt-on-completion handshake eliminates host resources utilization during read operations Write FIFO with variable size and configurable thresholds to enable non-blocking operations and prevent back-pressure propagation from card to host Supports posted write operations Supports SDIO IRQ signaling Implements multi-block read and write commands with internal STOP command generation (CMD12) for enhanced throughput Supports any data block length Supports fast and slow SD cards. SD clock frequency: 0-50+MHz Supports hot card insertion and removal SD/SDIO/MMC/SPI identification flow implemented by hardware Provides command port interface for direct access to the SD/MMC devices and for I/O access to SDIO devices Features zero-wait-states on SD bus Wide range of configuration options to fine-tune the core according to the system specifications and demands Wide range of mask able interrupt events, such as card detection, block transfer termination, command completion, error detection end many more No dedicated local memory required Download Product Brief

I2C Master and Slave I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. The interface defines 3 transmission speeds: Normal: 100Kbps Fast: 400Kbps High speed: 3.5Mbps Features: Compatible with Philips I2C standard Multimaster Operation Software programmable clock frequency Clock Stretching and Wait state generation Software programmable acknowledge bit Interrupt or bit-polling driven byte-by-byte data-transfers Arbitration lost interrupt, with automatic switching from master to slave Called as Slave interrupt Start/Stop/Repeated Start generation Acknowledge bit generation/detection Start/Stop detection Bus busy detection Supports 7 and 10bit addressing mode in both master and slave modes Operates from a wide range of input clock frequencies Static synchronous design Fully synthesizable

USB 2.0 Device IP Core A USB 2.0 Device IP Core that provides high performance small footprint solution for quick and easy implementation of a USB Device interface. USB 2.0 high performance operation UTMI+ L2 Interface, ULPI 1.1 wrapper and FS only transceiver interface available Full USB peripheral support High Speed and Full Speed mode support Up to 16 endpoints Bulk, interrupt and isochronous transfers Slave and Master System Interface No dedicated local memory required Compact and cost-effective solution for SoC Download Product Brief

Reed Solomon Encoder IP Core A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error correction. It can be targeted for both ASIC and FPGA technologies. Supports different Reed-Solomon coding standards Code rate can be dynamically varied Parameterizable bits per symbol (M) Programmable codeword length (NVAL) with parameterizable maximum value (N) Programmable number of errors (TVAL) with parameterizable maximum value (T) Shortened codes supported (NVAL,TVAL) User configured primitive field polynomial User configured generator polynomial Synchronous design Low latency - 2 cycles Single symbol rate clock Download Product Brief

Reed Solomon Decoder IP Core A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error correction. It can be targeted for both ASIC and FPGA technologies. Continuous, very high-speed, time-domain Reed-Solomon decoding algorithm. Supports different Reed-Solomon coding standards. Code rate can be dynamically varied Parameterizable bits per symbol (M). Programmable codeword length (NVAL) with parameterizable maximum value (N). Programmable number of errors (TVAL) with parameterizable maximum value (T). Shortened codes supported (NVAL,TVAL). User configured primitive field polynomial. User configured generator polynomial. Synchronous design. Predictable decoder latency. Single or Multiple symbol rate clock (CR). Status and performance monitoring signals Download Product Brief

AMBA AHB - WISHBONE Wrapper IP Core This IP Core consists of an AMBA AHB to WISHBONE and a WISHBONE to AMBA AHB interface 'wrappers'. It is fully AMBA 2.0 and WISHBONE Rev B3 compliant.

USB 2.0 On-The-Go IP Core A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB device. This USB IP Core supports both Low Speed, Full Speed and High Speed transfers and automatic line speed negotiation. Features Include: True Dual-Role capability UTMI+ L2 Interface and ULPI 1.1 wrapper available OTG high performance host mode Full USB peripheral capability Session request protocol support Host negotiation protocol support Low Speed (LS), Full Speed (FS) and High Speed (HS) modes supported Up to 16 endpoints Bulk, interrupt and isochronous transfers Slave and Master WISHBONE i/f (AMBA wrappers available) No dedicated local memory required Compact and cost-effective solution for SoC Download Product Brief OTG Evaluation Kit Brochure

16 Bit RISC DSP Soft IP Core A 16 bit true RISC Architecture Digital Signal Processor for embedded applications that require high performance in a small form factor with ultra low power consumption. Some of the highlights are: Fully Configurable Data and Address bus width (8-64 bit) Up to 128 General Purpose Registers Windowed Register File (up to 15 windows) Two Address generators with 8 Address and 8 Mask Registers each, Circular Buffer support Standard DSP operation such as MUL, MAC, DIVide, REPeat instructions Extensible Instruction Set Separate Instruction and Data buses Two Peripheral Buses Low Power Architecture Variable size Hardware Stack 60 Instructions Default Instruction Set Built in Instruction Decryption 16 Interrupts; 1 NMI; 32 Traps 128 GPIO (optional: UART, PCM, SPI) To many features to list them all ! Please download the product brief for more details ! Download Product Brief

16 Bit RISC MCU Soft IP Core A 16 bit true RISC Architecture Microcontroller for embedded applications that require high performance in a small form factor with ultra low power consumption. Some of the highlights are: Fully Configurable Data and Address bus width (8-64 bit) Up to 128 General Purpose Registers Windowed Register File (up to 15 windows) Extensible Instruction Set Separate Instruction and Data buses Low power architecture Variable size Hardware Stack 51 instructions default instruction set Built in instruction decryption 16 Interrupts; 1 NMI; 32 Traps 128 GPIO (optional: UART, I2C, SPI ) To many features to list them all ! Please download the product brief for more details ! Download Product Brief

Enhanced AES (Rijndael) IP Core FIPS-197 Compliant. Encrypt and decrypt modules with 128, 192 and 256 bit keys. Various versions are available, from small area to high performance, up to 34Gbit/sec in 0.18u. The following building blocks are available for Enhanced AES IP Core: Data Path Module, fully pipelined (single stage) Data Path Module, fully pipelined (dual stage) Static key module (128, 192, 256 bit) Dynamic key module (128, 192, 256 bit) Notes: - Data path modules can perform a full cypher/inverse cypher operation every clock cycle. The single stage pipeline version has a latency of 14 cycles, the dual stage pipeline of 24 cycles. - Static key modules need 12 cycles to expand a key, dynamic key modules can generate a new key every clock cycle. Download Product Brief

Enhanced Floating Point Unit Fully IEEE 754 Compliant. Parameterizable Architecture: Single Precision (32 bit) Extended Single Precision (44 bit) Double Precision (64 bit) Extended Double Precision (80 bit) Any other user selected format The enhanced floating point unit consists of: Floating Point Add/Subtract Unit (fasu) Floating Multiply Unit (fmul) Floating Point Divide Unit (fdiv) Floating Point Compare Unit (fcmp) Integer to Floating Point Conversion (i2fp) Floating Point to Integer Conversion (fp2i) Available with any number of pipeline stages desired. Any desired clock frequency. Download Product Brief

USB 2.0 On-The-Go IP Core A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB device. Fully USB 2.0 and USB 2.0 OTG Supplement Compliant. Features Include: True Dual-Role capability OTG host mode capability Full USB peripheral capability Session request protocol support Host negotiation protocol support Full Speed mode support Up to 16 endpoints Bulk, interrupt and isochronous transfers Embedded MCU interface Compact and cost-effective solution for SoC Download Product Brief